In today's semiconductor integrated circuit devices, an enormous number of semiconductor devices are formed on a common substrate, and a multilayer interconnection structure is used to interconnect these semiconductor devices.
In the multilayer interconnection structure, interlayer insulating films having interconnection patterns forming interconnection layers embedded therein are stacked in layers.
In this multilayer interconnection structure, a lower interconnection layer and an upper interconnection layer are connected with a via contact formed in the interlayer insulating film.
In particular, in recent ultra-microfabricated, ultra-high speed semiconductor devices, low dielectric constant films (so-called low-k films) are used as interlayer insulating films in order to reduce the problem of signal delay (RC delay) in the multilayer interconnection structure. At the same time, patterns of copper (Cu), which is low in resistance, are used as interconnection patterns.
In the multilayer interconnection structure thus having Cu interconnection patterns embedded in low dielectric constant interlayer insulating films, a process preforming a trench or via hole in an interlayer insulating film, a so-called damascene or dual-damascene process, is employed because it is difficult to pattern a Cu layer by dry etching. In the damascene or dual-damascene process, the trench or via hole thus formed is filled with a Cu layer, and an excessive portion of the Cu layer on the interlayer insulating film is thereafter removed by chemical-mechanical polishing (CMP).
At this point, if the Cu interconnection pattern comes into direct contact with the interlayer insulating film, Cu atoms are diffused into the interlayer insulating film to cause problems such as a short-circuit. Accordingly, as a common practice, the sidewall and bottom surfaces of the trench or via hole where the Cu interconnection pattern is formed are covered with a conductive diffusion barrier, or a so-called barrier metal film, and the Cu layer is deposited on the barrier metal film. Common examples of the barrier metal film include refractory metals such as tantalum (Ta), titanium (Ti), and tungsten (W) and conductive nitrides of these refractory metals.
On the other hand, in recent ultra-microfabricated, ultra-high speed semiconductor devices of the 45 nm generation or a later generation, the size of a trench or via hole formed in interlayer insulating films is extremely reduced with progress in microfabrication.
As a result, in order to achieve a desired reduction in interconnect resistance using such a barrier metal film having high resistivity, the thickness of the barrier metal film formed on the fine trench or via hole is reduced as much as possible.
On the other hand, the sidewall and bottom surfaces of the trench or via hole are covered with the barrier metal film.
With respect to this a situation, Japanese Laid-Open Patent Publication No. 2005-277390 discloses covering a trench or via hole formed in an interlayer insulating layer directly with a copper-manganese alloy layer (Cu—Mn alloy layer).
Japanese Laid-Open Patent Publication No. 2005-277390 discloses forming a manganese silicon oxide layer having a thickness of 2 nm to 3 nm and a composition of MnSixOy as a diffusion barrier layer at the interface between such a Cu—Mn alloy layer and an interlayer insulating film through the self-formation reaction of Mn in the Cu—Mn alloy layer and Si and oxygen in the interlayer insulating film.
According to this technique, however, there is the problem of insufficient adhesion to a Cu film due to the MnSixOy composition of the self-formed layer and a low concentration of a metal element included in the film.
Therefore, Japanese Laid-Open Patent Publication No. 2007-027259 discloses a structure where a Cu—Mn alloy layer and a barrier metal film of a refractory metal such as Ta or Ti are combined.
With such a combination structure of a Cu—Mn alloy layer and a barrier metal film of a refractory metal such as Ta or Ti, a preferable feature of increased resistance to oxidation is also obtained for the following reason.
In these years, it has been proposed to use a porous low dielectric constant film as a low dielectric constant material forming an interlayer insulating film in order to avoid signal delay (RC delay). However, such a porous low dielectric constant material is low in density so as to be easily damaged by plasma processing at the time of manufacture. The damaged film is more likely to have moisture adsorbed to its surface or inside.
Therefore, a barrier metal film formed on such a porous low dielectric constant film is likely to be oxidized because of the moisture adsorbed inside the porous low dielectric constant film, so that the performance of the barrier metal film as a diffusion barrier and its adhesion to a Cu interconnection layer or via plug are likely to be degraded.
However, using the above-described Cu—Mn alloy layer in such a structure causes Mn in the Cu—Mn alloy layer to react with an oxidized portion of the barrier metal film so as to make it possible to maintain the performance of the barrier metal film as a diffusion barrier and its high adhesion to a Cu interconnection layer or via plug. Therefore, studies have been made of forming Cu interconnection layers or via plugs by a damascene or dual-damascene process using such a Cu—Mn alloy layer.